High performance embedded architectures and compilers : second international conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007 : proceedings / Koen De Bosschere [and others] (eds.).
"This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in Januar 2007.; The 19 revised full papers presented together with 1 invited keynote paper were carefully review...
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| Format: | Ebook |
| Language: | English |
| Published: |
Berlin ; New York :
Springer,
[2007]
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| Series: | Lecture notes in computer science ;
4367. |
| Subjects: | |
| Online Access: | Springer eBooks Table of contents |
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| 245 | 1 | 0 | |a High performance embedded architectures and compilers : |b second international conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007 : proceedings / |c Koen De Bosschere [and others] (eds.). |
| 246 | 3 | 0 | |a HiPEAC 2007 |
| 264 | 1 | |a Berlin ; |a New York : |b Springer, |c [2007] | |
| 264 | 4 | |c ©2007 | |
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| 490 | 1 | |a Lecture notes in computer science, |x 0302-9743 ; |v 4367 | |
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | 0 | |t Invited Program: -- |t Keynote: Insight, Not (Random) Numbers: An Embedded Perspective / |r Thomas M. Conte -- |t I Secure and Low-Power Embedded Memory Systems: -- |t Compiler-Assisted Memory Encryption for Embedded Processors / |r Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy -- |t Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems / |r Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson -- |t Applying Decay to Reduce Dynamic Power in Set-Associative Caches / |r Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras -- |t II Architecture/Compiler Optimizations for Efficient Embedded Processing: -- |t Virtual Registers: Reducing Register Pressure Without Enlarging the Register File / |r Jun Yan, Wei Zhang -- |t Bounds Checking with Taint-Based Analysis / |r Weihaw Chuang, Satish Narayanasamy, Brad Calder, Ranjit Jhala -- |t Reducing Exit Stub Memory Consumption in Code Caches / |r Apala Guha, Kim Hazelwood, Mary Lou Soffa -- |t III Adaptive Microarchitectures: -- |t Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling / |r Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh -- |t Fetch Gating Control Through Speculative Instruction Window Weighting / |r Hans Vandierendonck, André Seznec -- |t Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches / |r Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares -- |t Branch History Matching: Branch Predictor Warmup for Sampled Simulation / |r Simon Kluyskens, Lieven Eeckhout -- |t Sunflower : Full-System, Embedded Microarchitecture Evaluation / |r Phillip Stanley-Marbell, Diana Marculescu -- |t Efficient Program Power Behavior Characterization / |r Chunling Hu, Daniel A. Jiménez, Ulrich Kremer -- |t Generation of Efficient Embedded Applications: -- |t Performance/Energy Optimization of DSP Transforms on the XScale Processor / |r Paolo D’Alberto, Markus Püschel, Franz Franchetti -- |t Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms / |r Klaas L. Hofstra, Sabih H. Gerez -- |t A Throughput-Driven Task Creation and Mapping for Network Processors / |r Lixia Liu, Xiao-Feng Li, Michael Chen, Roy D. C. Ju -- |t Optimizations and Architectural Tradeoffs for Embedded Systems: -- |t MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization / |r Grigori Fursin, John Cavazos, Michael O’Boyle, Olivier Temam -- |t Evaluation of Offset Assignment Heuristics / |r Johnny Huynh, José Nelson Amaral, Paul Berube, Sid-Ahmed-Ali Touati -- |t Customizing the Datapath and ISA of Soft VLIW Processors / |r Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl -- |t Instruction Set Extension Generation with Considering Physical Constraints / |r I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jyh-Jiun Shann. |
| 520 | |a "This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in Januar 2007.; The 19 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on secure and low-power embedded memory systems, architecture/compiler optimizations for efficient embedded processing, adaptive microarchitectures, architecture evaluation techniques, generation of efficient embedded applications, as well as optimizations and architectural tradeoffs for embedded systems."--Publisher description. | ||
| 588 | |a Machine converted from AACR2 source record. | ||
| 650 | 0 | |a Compilers (Computer programs) |v Congresses |9 698245 | |
| 650 | 0 | |a Computer architecture |v Congresses |9 629087 | |
| 650 | 0 | |a Embedded computer systems |v Congresses |9 765283 | |
| 700 | 1 | |a Bosschere, Koen de, |e author. |9 299479 | |
| 776 | 1 | 8 | |w (OCoLC)79447619 |
| 830 | 0 | |a Lecture notes in computer science ; |v 4367. |x 0302-9743. |9 291610 | |
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