Designing reliable and efficient networks on chips / Srinivasan Murali.
"Developing No C based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, anothe...
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| Main Author: | |
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| Format: | Ebook |
| Language: | English |
| Published: |
[Dordrecht] :
Springer,
[2009]
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| Series: | Lecture notes in electrical engineering ;
v. 34. |
| Subjects: | |
| Online Access: | Springer eBooks |
| Summary: | "Developing No C based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for No Cs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chipsis to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during No C design."--Publisher's website. |
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| Physical Description: | 1 online resource (x, 198 pages) : illustrations (some colour). |
| Bibliography: | Includes bibliographical references. |
| ISBN: | 1402097565 9781402097560 1282364065 9781282364066 1402097573 9781402097577 |